In applications such as plesiochronous or isochronous telecommunication systems, it is desirable to make adjustments to the phase of a clock in order to synchronize the clock with an external reference. It may also be necessary in these applications to generate a positive or negative frequency adjustment to the clock. The phase and frequency adjustments may be accomplished by periodically adjusting the phase of the clock by advancing or retarding the phase of the clock.
In the past, analog circuits such as phase locked loops, mixers and other electrical circuits having inductors and capacitors were used to offset the frequency and phase of a clock. These analog circuits adjusted the phase and frequency directly or smoothed out phase discontinuities by adding or dropping clock pulses. A second approach used in the past to provide a clock with a phase and frequency matching an external reference was to synthesize a clock with the desired phase and frequency characteristics of the external reference. This was achieved by dividing an internal clock operating at a higher speed clock. By changing the modulus of the divider, the phase or frequency of the synthesized clock could be adjusted. Both these approaches, however, suffered from various drawbacks. The analog circuits used to offset the frequency and phase of a clock could not be constructed using digital circuit components. In order to implement the analog circuits, special design consideration had to be given to the placement of the circuit components. Alternatively, the analog circuits had to be placed off-chip. The approach of synthesizing a clock with the desired phase and frequency characteristics of the external reference required a clock operating at a much higher frequency than the external reference. Implementing a high speed clock was difficult and costly.
Thus, what is needed is an efficient and effective method and apparatus for adjusting the phase and frequency of a period wave.